Semiconductor device and manufacturing method thereof
US7397094B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 26, 2005 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | Nov 29, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
To provide a semiconductor device that enables to suppress a defect density of a gate insulating film of an MISFET, gain a sufficient electric characteristic thereof, and make an Equivalent Oxide Thickness (EOT) of the gate insulating film 1.0 nm or less. The MISFETs are formed to have the gate insulating film formed on a main surface of a silicon substrate, and a gate electrode formed on the gate insulating film, wherein the gate insulating film includes a metal silicate layer formed by a metal oxide layer and a silicon oxide layer and the metal silicate layer is formed so as to have concentration gradients of metal and silicon from a silicon substrate side toward a gate electrode side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.