Logic block control architectures for programmable logic devices

US7397276B1 · kind B1 · utility

Assignee

• Lattice Semiconductor Corporation · US

Inventors

• Om P. Agrawal · Los Altos, US
• Xiaojie He · Austin, US
• Sajitha Wijesuriya · Macungie, US
• Barry Britton · Orefield, US
• Ming H. Ding · San Jose, US
• Jun Zhao · Mianyang, CN

Key dates

• Filing date: Jun 2, 2006
• Grant date: Jul 8, 2008
• Expiry date: Aug 1, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/17728
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks, with each of the logic block slices having at least a first and a second slice each having at least a first lookup table. At least one of the programmable logic blocks includes at least a first logic block slice, a second logic block slice, and a third logic block slice, with the first logic block slice being a logic block slice type different from the second logic block slice, and the third logic block slice being a logic block slice type different from the first and second logic block slices. Control logic provides at a programmable logic block level bundled and/or unbundled control signals at a logic block slice level for at least two of the logic block slices.