Embedded strain layer in thin SOI transistors and a method of forming the same

US7399663B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Jan Hoentschel · Dresden, DE
• Andy Wei · Queensbury, US
• Manfred Horstmann · Dresden, DE
• Thorsten Kammler · Radeberg, DE

Key dates

• Filing date: Aug 23, 2006
• Grant date: Jul 15, 2008
• Expiry date: Aug 23, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/822

Abstract

By forming a deep recess through the buried insulating layer and re-growing a strained semiconductor material, an enhanced strain generation mechanism may be provided in SOI-like transistors. Consequently, the strain may also be efficiently created by the embedded strained semiconductor material across the entire active layer, thereby significantly enhancing the performance of transistor devices, in which two channel regions may be defined.