Patent · US Expired

Charge-trapping memory device and methods for operating and manufacturing the cell

US7402490B2 · kind B2 · utility

2Cited by

8References

22Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thomas Mikolajick · Birkenfeld, DE
Hans Reisinger · Grünwald, DE
Josef Willer · Riemerling, DE
Corvin Liaw · Birkenfeld, DE

Key dates

Filing date	Oct 19, 2005
Grant date	Jul 22, 2008
Priority date	—
Expiry date	Dec 28, 2025

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/037
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.