Method of forming through-silicon vias with stress buffer collars and resulting devices
US7402515B2 · kind B2 · utility
332Cited by
5References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2005 |
| Grant date | Jul 22, 2008 |
| Priority date | — |
| Expiry date | Jun 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.