Post high voltage gate oxide pattern high-vacuum outgas surface treatment
US7402524B2 · kind B2 · utility
0Cited by
8References
11Claims
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Key dates
| Filing date | Dec 2, 2005 |
| Grant date | Jul 22, 2008 |
| Priority date | — |
| Expiry date | Feb 14, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.