Methods and apparatus for thermal management in a multi-layer embedded chip structure
US7405102B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2006 |
| Grant date | Jul 29, 2008 |
| Priority date | — |
| Expiry date | Sep 16, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10416
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-layer structure (102) includes a first build-up layer structure (202) configured to connect to a heat-generating module (120), a second build-up layer structure (206) configured to connect to a substrate, and a middle layer (204) provided between the first build-up layer structure and the second build-up layer structure, the middle layer including at least one semiconductor component (110) and a heat spreader (130). A first set of thermal vias (210) extend through the first build-up layer structure to the heat spreader, and a second set of thermal vias (2100 extend through the second build-up layer structure to the heat spreader, wherein at least a portion of the first set of thermal vias is in thermal contact with the heat-generating module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.