Stacked multi-gate transistor design and method of fabrication

US7407847B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Brian S. Doyle · Portland, US
• Titash Rakshit · Austin, US
• Robert S. Chau · Beaverton, US
• Suman Datta · Beaverton, US
• Justin K. Brask · Portland, US
• Uday Shah · Portland, US

Key dates

• Filing date: Mar 31, 2006
• Grant date: Aug 5, 2008
• Expiry date: Aug 18, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0245

Abstract

A multi-body thickness (MBT) field effect transistor (FET) comprises a silicon body formed on a substrate. The silicon body may comprise a wide section and a narrow section between the wide section and the substrate. The silicon body may comprise more than one pair of a wide section and a narrow section, each pair being located at a different height of the silicon body. The silicon body is surrounded by a gate material on three sides. The substrate may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The MBT-FET combines the advantages of a wide fin device and a narrow fin device.