Isolation structure configurations for modifying stresses in semiconductor devices
US7410858B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2006 |
| Grant date | Aug 12, 2008 |
| Priority date | — |
| Expiry date | May 19, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.