System and method for providing a dual via architecture for thin film resistors

US7410879B1 · kind B1 · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

• Rodney Hill · San Jose, US
• Victor Torres · Clifton Park, US
• Michael Burger · Aliso Viejo, US
• Terry Lines · Mansfield, US

Key dates

• Filing date: Aug 3, 2005
• Grant date: Aug 12, 2008
• Expiry date: Nov 15, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/474

Abstract

A buried thin film resistor having end caps defined by a dielectric mask is disclosed. A thin film resistor is formed on an integrated circuit substrate. A resistor protect layer is formed over the thin film resistor. First and second portions of a first dielectric material are formed over the resistor protect layer over the first and second ends of the thin film resistor. The resistor protect layer is then wet etched using the first and second portions of the first dielectric material as a hard mask. Then a second dielectric layer is deposited. A first via mask and etch process is used to etch vias down to the underlying portions of the resistor protect layer over the ends of the thin film resistor. A second via mask and etch process is used to etch substrate vias to an underlying conductor layer.