CMOS silicide metal gate integration
US7411227B2 · kind B2 · utility
5Cited by
16References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2006 |
| Grant date | Aug 12, 2008 |
| Priority date | — |
| Expiry date | Apr 19, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.