Semiconductor integrated circuit device
US7411301B2 · kind B2 · utility
8Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2005 |
| Grant date | Aug 12, 2008 |
| Priority date | — |
| Expiry date | Mar 3, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.