System including a host connected to a plurality of memory modules via a serial memory interconnect
US7421525B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2004 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Nov 26, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.