Methods for forming interconnects in vias and microelectronic workpieces including such interconnects
US7425499B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2004 |
| Grant date | Sep 16, 2008 |
| Priority date | — |
| Expiry date | Jan 19, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76898
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for forming interconnects in blind vias or other types of holes, and microelectronic workpieces having such interconnects. The blind vias can be formed by first removing the bulk of the material from portions of the back side of the workpiece without thinning the entire workpiece. The bulk removal process, for example, can form a first opening that extends to an intermediate depth within the workpiece, but does not extend to the contact surface of the electrically conductive element. After forming the first opening, a second opening is formed from the intermediate depth in the first opening to the contact surface of the conductive element. The second opening has a second width less than the first width of the first opening. This method further includes filling the blind vias with a conductive material and subsequently thinning the workpiece from the exterior side until the cavity is eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.