Methods of fabricating passive element without planarizing
US7427550B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2006 |
| Grant date | Sep 23, 2008 |
| Priority date | — |
| Expiry date | Jul 28, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.