Method for performing full-chip manufacturing reliability checking and correction
US7434195B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2005 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | Feb 2, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70441
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of generating a mask for use in an imaging process pattern. The method includes the steps of: (a) obtaining a desired target pattern having a plurality of features to be imaged on a substrate; (b) simulating a wafer image utilizing the target pattern and process parameters associated with a defined process; (c) defining at least one feature category; (d) identifying features in the target pattern that correspond to the at least one feature category, and recording an error value for each feature identified as corresponding to the at least one feature category; and (e) generating a statistical summary which indicates the error value for each feature identified as corresponding to the at least one feature category.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.