Low temperature methods of forming back side redistribution layers in association with through wafer interconnects
US7435620B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2007 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Jul 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/09701
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Low temperature processed back side redistribution lines (RDLs) are disclosed. Low temperature processed back side RDLs may be electrically connected to the active surface devices of a semiconductor substrate using through wafer interconnects (TWIs). The TWIs may be formed prior to forming the RDLs, after forming the RDLs, or substantially simultaneously to forming the RDLs. The material for the back side RDLs and various other associated materials, such as dielectrics and conductive via filler materials, are processed at temperatures sufficiently low so as to not damage the semiconductor devices or associated components contained on the active surface of the semiconductor substrate. The low temperature processed back side RDLs of the present invention may be employed with optically interactive semiconductor devices and semiconductor memory devices, among many others. Semiconductor devices employing the RDLs of the present invention may be stacked and electrically connected theretogether.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.