Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity
US7435676B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2006 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Oct 7, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76829
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Interconnect structures possessing an organosilicate glass interlayer dielectric material with minimal stoichiometeric modification and optionally an intact organic adhesion promoter for use in semiconductor devices are provided herein. The interconnect structure is capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the stack compared with that of those conventionally employed because of the use of a sacrificial polymeric material deposited onto the dielectric and optional organic adhesion promoter during the barrier open step done prior to ashing the patterning material. This sacrificial film protects the dielectric and optional organic adhesion promoter from modification/consumption during the subsequent ashing step during which the polymeric film is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.