Apparatus and method for selectively recessing spacers on multi-gate devices
US7435683B2 · kind B2 · utility
20Cited by
32References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2006 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Jan 25, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
Abstract
Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.