Method of forming a low-K dual damascene interconnect structure

US7435685B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Gerardo Delgadino · Fremont, US
• Yan Ye · Saratoga, US
• Neungho Shin · San Ramon, US
• Yunsang Kim · San Jose, US
• Li-Qun Xia · Santa Clara, US
• Tzu-Fang Huang · San Jose, US
• Lihua Huang · Tangxia, CN
• Joey Chiu · Kaohsiung, TW
• Xiaoye Zhao · Mountain View, US
• Fang Tian · Beijing, CN
• Wen Zhu · Sunnyvale, US
• Ellie Yieh · San Jose, US

Key dates

• Filing date: Sep 13, 2006
• Grant date: Oct 14, 2008
• Expiry date: Jan 26, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76813
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.