Forming a type I heterostructure in a group IV semiconductor
US7435987B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2007 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Apr 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
In one embodiment, the present invention includes a method for forming a transistor that includes forming a first buffer layer of silicon germanium tin (SiGe(Sn)) on a silicon (Si) substrate, forming a barrier layer on the first buffer layer, the barrier layer comprising silicon germanium (Si1−xGex), and forming a quantum well (QW) layer on the barrier layer including a lower QW barrier layer formed of silicon germanium carbon (Si1−yGey(C)), a strained QW channel layer formed of germanium on the lower QW layer, and an upper QW barrier layer on the strained QW channel layer formed of Si1−zGez(C). Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.