Semiconductor package for encapsulating multiple dies and method of manufacturing the same
US7439098B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2005 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | Oct 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package comprises a silicon substrate having an insulative surface; a patterned metal layer, formed on the insulative surface of the silicon substrate; an insulation layer formed on the patterned metal layer, and the patterned metal layer being partially exposed for functioning as at least a set of the device attaching pads and ball attaching pads; at least a device electrically connected to the set of the device attaching pads; a sealing compound for covering portions of the insulative surface of the silicon substrate and encapsulating the devices; and a plurality of solder balls attached to the set of ball attaching pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.