Method and structure for integrating MIM capacitors within dual damascene processing techniques

US7439151B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Douglas D. Coolbaugh · Highland, US
• Timothy J. Dalton · Ridgefield, US
• Ebenezer E. Eshun · South Burlington, US
• Vincent J. McGahay · Poughkeepsie, US
• Anthony K. Stamper · Williston, US
• Kunal Vaed · Poughkeepsie, US

Key dates

• Filing date: Sep 13, 2006
• Grant date: Oct 21, 2008
• Expiry date: Jan 16, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer having a first dielectric capping layer formed thereon. An upper ILD layer is formed over the lower ILD layer, and a via and upper line structure are defined within the upper ILD layer. The via and upper line structure are filled with a planarizing layer, followed by forming and patterning a resist layer over the planarizing layer. An upper capacitor electrode structure is defined in the upper ILD layer corresponding to a removed portion of the resist. The via, upper line structure and upper capacitor electrode structure are filled with conductive material, wherein a MIM capacitor is defined by the lower capacitor electrode, first dielectric capping layer and upper capacitor electrode structure.