Stress enhanced CMOS circuits and methods for their fabrication

US7442601B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Gen Pei · Yorktown Heights, US
• Scott Luning · San Francisco, US
• Johannes M. van Meer · Middleton, US

Key dates

• Filing date: Sep 18, 2006
• Grant date: Oct 28, 2008
• Expiry date: Sep 22, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/01

Abstract

A stress enhanced CMOS circuit and methods for its fabrication are provided. One fabrication method comprises the steps of forming an NMOS transistor and a PMOS transistor adjacent the NMOS transistor in a channel width direction, the PMOS transistor and the NMOS transistor separated by an isolation region. A compressive stress liner is deposited overlying the transistors and the isolation region and is etched to remove the compressive stress liner from the NMOS transistor and from a portion of the isolation region. A tensile stress liner is deposited overlying the transistors, the isolation region, and the compressive stress liner and is etched to remove a portion of the tensile stress liner overlying a portion of the compressive stress liner and to leave the tensile stress liner overlying the NMOS transistor, the isolation region, and a portion of the compressive stress liner.