Wafer level chip scale package (WLCSP) with high reliability against thermal stress
US7446405B2 · kind B2 · utility
5Cited by
4References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 29, 2006 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | May 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer level chip scale package includes a semiconductor chip having a plurality of pads; a lower insulation layer having a high Young's modulus of 1˜5 GPa formed on the semiconductor chip to expose the plurality of pads; a plurality of metal patterns formed on the lower insulation layer to be connected to the respective pads; an upper insulation layer having a high Young's modulus of 1˜5 GPa formed on the lower insulation layer and the metal patterns to partially expose the metal patterns; and a plurality of solder balls formed on exposed portions of the metal patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.