Low voltage column decoder sharing a memory array p-well
US7447071B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2006 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Apr 26, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of memory sub-arrays are formed in a p-well region. Each of the memory sub-arrays has at least one first-level column decoder that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder is formed outside of the p-well region and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers. During a memory erase mode of operation, a high voltage is provided to bias the p-well region and a plurality of high-voltage switches are activated to provide a high voltage to gate terminals of the selector transistor in the first-level column decoders. One or more intermediate-level column decoders are formed as low-voltage selector transistors in the p-well between the first-level column decoder and the last-level column decoder. Each of the intermediate-level column decoders also has a high-voltage switch that is activated during a memory erase mode of operation to provide a high voltage to gate terminals of the intermediate-level column decoders.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.