Selective program voltage ramp rates in non-volatile memory
US7447086B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2007 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Oct 2, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.