Data processing system, processor and method of data processing that reduce store queue entry utilization for synchronizing operations
US7454580B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2006 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Jan 12, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/544
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a processor core and a memory subsystem. The memory subsystem includes a store queue having a plurality of entries, where each entry includes an address field for holding the target address of store operation, a data field for holding data for the store operation, and a virtual sync field indicating a presence or absence of a synchronizing operation associated with the entry. The memory subsystem further includes a store queue controller that, responsive to receipt at the memory subsystem of a sequence of operations including a synchronizing operation and a particular store operation, places a target address and data of the particular store operation within the address field and data field, respectively, of an entry in the store queue and sets the virtual sync field of the entry to represent the synchronizing operation, such that a number of store queue entries utilized is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.