Verifying a process margin of a mask pattern using intermediate stage models
US7458058B2 · kind B2 · utility
1Cited by
16References
18Claims
0Family size
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Key dates
| Filing date | Jun 10, 2005 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Apr 17, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Verifying a process margin for a mask pattern includes receiving the mask pattern for patterning features on a semiconductor wafer. The mask pattern is modified according to a wafer pattern model operable to estimate a wafer pattern resulting from the mask pattern. An intermediate stage model is selected to apply to a portion of the mask pattern, where the intermediate stage model is operable to estimate an intermediate stage of the wafer pattern. A process margin of the portion is verified by selecting a test of the intermediate stage model, and performing the test on the portion to verify the process margin of the portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.