Methods of fabricating vertical channel field effect transistors having insulating layers thereon
US7459359B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2006 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Dec 15, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6213
Abstract
A method of forming a field effect transistor includes forming a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and forming an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The method may also include forming a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, forming a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and forming a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.