Methods of forming dual-damascene interconnect structures using adhesion layers having high internal compressive stresses
US7459388B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 6, 2006 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Nov 7, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming interconnect structures include forming a first metal wiring pattern on a first dielectric layer and forming a capping layer (e.g., SiCN layer) on the first copper wiring pattern. An adhesion layer is deposited on the capping layer, using a first source gas containing octamethylcyclotetrasilane (OMCTS) at a volumetric flow rate in a range from about 500 sccm to about 700 sccm and a second gas containing helium at a volumetric flow rate in a range from about 1000 to about 3000 sccm. The goal of the deposition step is to achieve an adhesion layer having an internal compressive stress of greater than about 150 MPa therein, so that the adhesion layer is less susceptible to etching/cleaning damage and moisture absorption during back-end processing steps. Additional dielectric and metal layers are then deposited on the adhesion layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.