Circuitry and method for accessing an associative cache with parallel determination of data and data availability
US7461208B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2005 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Apr 25, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6082
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for accessing an associative cache is provided. The circuit includes data selection circuitry and an outcome parallel processing circuit both in communication with the associative cache. The outcome parallel processing circuit is configured to determine whether an accessing of data from the associative cache is one of a cache hit, a cache miss, or a cache mispredict. The circuit further includes a memory in communication with the data selection circuitry and the outcome parallel processing circuit. The memory is configured to store a bank select table, whereby the bank select table is configured to include entries that define a selection of one of a plurality of banks of the associative cache from which to output data. Methods for accessing the associative cache are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.