Low tunnel barrier insulators
US7465983B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2007 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Feb 20, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0416
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.