Method for programming and erasing an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits
US7466591B2 · kind B2 · utility
3Cited by
10References
6Claims
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Key dates
| Filing date | Jun 1, 2006 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Jan 31, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.