Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress

US7470972B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Jack T. Kavalieros · Portland, US
• Justin K. Brask · Portland, US
• Mark L. Doczy · Beaverton, US
• Matthew V. Metz · Portland, US
• Suman Datta · Beaverton, US
• Brian S. Doyle · Portland, US
• Robert S. Chau · Beaverton, US
• Everett Wang · San Jose, US
• Philippe Matagne · Beaverton, US
• Lucian Shifren · San Jose, US
• Been-Yih Jin · Lake Oswego, US
• Mark Stettler · Hillsboro, US
• Martin D. Giles · Portland, US

Key dates

• Filing date: Mar 11, 2005
• Grant date: Dec 30, 2008
• Expiry date: Apr 14, 2025

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/933

Abstract

A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.