Memory transistor gate oxide stress release and improved reliability
US7471541B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2007 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Jun 22, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory transistor gates to read signals are significantly reduced. In some embodiments, after a short read cycle, the content of the memory cell is latched and maintained as long as the subsequent read attempts are directed to the same memory cell. In these embodiments the read cycle need only be long enough to latch the memory content of the cell, and as long as the subsequent read attempts target the same memory cell the latched value will be used instead of repeating the read process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.