Providing stress uniformity in a semiconductor device

US7473623B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Jian Chen · San Jose, US
• Mark W. Michael · Cedar Park, US

Key dates

• Filing date: Jun 30, 2006
• Grant date: Jan 6, 2009
• Expiry date: Aug 31, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A method includes forming a plurality of functional features on a semiconductor layer in a first region. A non-functional feature corresponding to the functional feature is formed adjacent at least one of the functional features disposed on a periphery of the region. A stress-inducing layer is formed over at least a portion of the functional features and the non-functional feature. A device includes a semiconductor layer, a first dummy gate electrode, and a stress-inducing layer. The plurality of transistor gate electrodes is formed above the semiconductor layer. The plurality includes at least a first end gate electrode, a second end gate electrode, and at least one interior gate electrode. The first dummy gate electrode is disposed proximate the first end gate electrode. The stress-inducing layer is disposed over at least a portion of the plurality of transistor gate electrodes and the first dummy gate electrode.