Equivalent gate count yield estimation for integrated circuit devices
US7477961B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2006 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Mar 6, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of modeling yield for semiconductor products includes determining expected faults for each of a plurality of library elements by running a critical area analysis on each of the library elements, and assessing, from the critical area analysis, an expected number of faults per unit area, and comparing the same to actual observed faults on previously manufactured semiconductor products. Thereafter, the expected number of faults for each library element is updated in response to observed yield. A database is established, which includes the die size and expected faults for each of the library elements. Integrated circuit product die size is estimated, and library elements to be used to create the integrated circuit die are selected. Fault and size data for each of the selected library elements are obtained, the adjusted estimated faults for each of the library elements are summed, and estimated yield is calculated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.