Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby

US7479421B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Jack T. Kavalieros · Portland, US
• Justin K. Brask · Portland, US
• Brian S. Doyle · Portland, US
• Uday Shah · Portland, US
• Suman Datta · Beaverton, US
• Mark L. Doczy · Beaverton, US
• Matthew V. Metz · Portland, US
• Robert S. Chau · Beaverton, US

Key dates

• Filing date: Sep 28, 2005
• Grant date: Jan 20, 2009
• Expiry date: Nov 2, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017

Abstract

A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.