Ring oscillator row circuit for evaluating memory cell performance
US7483322B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2007 |
| Grant date | Jan 27, 2009 |
| Priority date | — |
| Expiry date | Dec 22, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.