Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness

US7485537B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Herbert L. Ho · New Windsor, US
• Mahender Kumar · Hopewell Junction, US
• Qiqing C. Ouyang · Yorktown Heights, US
• Paul A. Papworth · Wappingers Falls, US
• Christopher D. Sheraw · Wappingers Falls, US
• Michael D. Steigerwalt · Newburgh, US

Key dates

• Filing date: Jul 20, 2006
• Grant date: Feb 3, 2009
• Expiry date: Dec 27, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

The present invention provides a a method of fabricating bipolar junction transistors (BJTs) on selected areas of a very thin buried oxide (BOX) using a conventional silicon-on-insulator (SOI) starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.