Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor
US7494856B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2006 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Apr 25, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6741
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor fabrication process includes forming an etch stop layer (ESL) overlying a buried oxide (BOX) layer and an active semiconductor layer overlying the ESL. A gate electrode is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors are formed on the ESL where the source/drain stressors strain the transistor channel. Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH4OH:H2O heated to a temperature of approximately 75° C. may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium. The source/drain stressors may be silicon germanium having a second percentage of germanium for P-type transistors, and they may be silicon carbon for N-type transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.