Interposer and test assembly for testing electronic devices
US7501839B2 · kind B2 · utility
26Cited by
27References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2006 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Dec 4, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10378
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test apparatus which uses a pair of substrates and housing to interconnect a host substrate (e.g., PCB) to an electronic device (e.g., semiconductor chip) to accomplish testing of the device. The apparatus includes a housing designed for being positioned on the PCB and have one of the substrates oriented therein during device engagement. The engaging contacts of the upper (second) substrate are sculpted to assure effective chip connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.