Feature dimension deviation correction system, method and program product

US7502660B2 · kind B2 · utility

Assignees

• International Business Machines Corporation · US
• TOKYO ELECTRON LIMITED · JP

Inventors

• David V. Horak · South Burlington, US
• Wesley C. Natzle · New Paltz, US
• Merritt Funk · Austin, US
• Kevin Lally · Austin, US
• Daniel Prager · Hopewell Junction, US

Key dates

• Filing date: Oct 2, 2007
• Grant date: Mar 10, 2009
• Expiry date: Oct 2, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L22/20
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A system, method and program product for correcting a deviation of a dimension of a feature from a target in a semiconductor process, are disclosed. The invention determines an origin of a deviation in a feature dimension from a target dimension regardless of whether it is based on processing or metrology. Adjustments for wafer processing variation of previous process tools can be fed forward, and adjustments for the process and/or integrated metrology tools may be fed back automatically during the processing of semiconductor wafers. The invention implements process reference wafers to determine the origin in one mode, and measurement reference wafers to determine the origin of deviations in another mode.