Process of forming a non-volatile memory cell including a capacitor structure

US7504302B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Leo Mathew · Austin, US
• Ramachandran Muralidhar · Austin, US
• Tab A. Stephens · Kyle, US

Key dates

• Filing date: Mar 18, 2005
• Grant date: Mar 17, 2009
• Expiry date: Jun 19, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

A non-volatile memory cell can include a substrate, an active region overlying the substrate, and a capacitor structure overlying the substrate. From a plan view, the capacitor structure surrounds the active region. In one embodiment, the non-volatile memory cell includes a floating gate electrode and a control gate electrode. The capacitor structure comprises a first capacitor portion, and the first capacitor portion comprises a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is electrically connected to the floating gate electrode, and the second capacitor electrode is electrically connected to the control gate electrode. A process for forming the non-volatile memory cell can include forming an active region over a substrate, and forming a capacitor structure over the substrate, wherein from a plan view, the capacitor structure surrounds the active region.