Etch singulated semiconductor package
US7507603B1 · kind B1 · utility
28Cited by
299References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2005 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | Mar 24, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In accordance with the present invention, there is provided various methods of simultaneously fabricating a plurality of semiconductor packages (e.g., cavity type semiconductor packages) wherein the singulation process is achieved using etching techniques as opposed to more conventional cutting techniques such as sawing or punching. Such etching techniques are inherently lower in cost and free from many of the defects induced by other cutting techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.