Through-wafer vias and surface metallization for coupling thereto

US7510907B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• John Heck · Berkeley, US
• Qing Ma · Saratoga, US
• Quan Tran · Fremont, US
• Tsung-Kuan A. Chou · San Jose, US
• Semeon Altshuler · Nesher, IL
• Boaz Weinfeld · Jerusalem, IL

Key dates

• Filing date: Jun 22, 2005
• Grant date: Mar 31, 2009
• Expiry date: Jul 27, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An apparatus and method of fabricating a through-wafer via. A first mask is formed over a first side of a first semiconductor die to define a first via area. A deep recess is etched through the first semiconductor die in the first via area and a blanket metal layer is formed over the first side including the deep recess. The blanket metal layer is removed from an outer surface of the first side of the first semiconductor die while retaining a portion of the blanket metal layer within the deep recess.