Patent · US Active

IC chip stress testing

US7512506B2 · kind B2 · utility

4Cited by

2References

14Claims

0Family size

Assignees

International Business Machines Corporation · US
Advanced Micro Devices, Inc. · US

Inventors

Oliver Aubel · Dresden, DE
Tom C. Lee · South Burlington, US
Deborah M. Massey · Jericho, US
Travis S. Merrill · Rutland, US
Stanley W. Polchlopek · Shelburne, US
Alvin W. Strong · South Burlington, US
Timothy D. Sullivan · Batavia, US

Key dates

Filing date	May 31, 2007
Grant date	Mar 31, 2009
Priority date	—
Expiry date	May 31, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/2879
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current Is to the line; and stress testing the line while applying the constant current Is such that the constant current Is is not altered by a resistance change due to an onset of electromigration.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.