Patent · US Active

Integrated circuit including sub-lithographic structures

US7514362B2 · kind B2 · utility

5Cited by

8References

11Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Cay-Uwe Pinnow · Birkenfeld, DE
Thomas Happ · Tarrytown, US
Michael Kund · Bad Aibling, DE
Gerhard Mueller · Meitingen, DE

Key dates

Filing date	Oct 26, 2005
Grant date	Apr 7, 2009
Priority date	—
Expiry date	Sep 16, 2026

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method which makes it possible to define in a patterning layer openings having a first dimension that is substantially less than the feature size that can be obtained lithographically includes applying a sacrificial layer made of a material that is different from that of the patterning layer in a predetermined layer thickness on the patterning layer. Afterward, a photoresist layer is applied on the surface of the sacrificial layer, and an opening having a second dimension is defined lithographically in the photoresist layer. Afterward, an etching angle is set in a manner dependent on the layer thickness of the sacrificial layer and also the first and second dimensions, and the sacrificial layer is etched at the etching angle set. Afterward, the patterning layer is etched, the sacrificial layer is removed and a filling material is introduced into the opening produced in the patterning layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.