Method for evaluating leakage effects on static memory cell access time
US7515491B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2007 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | Mar 14, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for evaluating leakage effects on static memory cell access time provides a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the states of other static memory cells connected to the same bitline as a static memory cell under test, the effect of leakage on the access time of the cell can be observed. The leakage effects can further be observed while varying the internal symmetry of the memory cell, operating the cell and observing changes in performance caused by the asymmetric operation. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.